Date: 5/25/04

SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2004 Sipex Corporation

9

Pin 12 — CE

output pin goes LOW only when CE

LOW and V

voltage. If CE

asserted, this output pin will stay low for

16

µs or until CE

occurs first.

Pin 13 — CE

input pin to the chip-enable gating circuit.

If this input pin is not used, connect it to

ground or V

Pin 14 — WDO — Watchdog Output. If WDI

remains HIGH or LOW longer than the

watchdog timeout period, this output pin

goes LOW and RESET is asserted for the

reset timeout period. This output pin returns

HIGH on the next transition at WDI.

This output pin remains HIGH if WDI is

unconnected.

Pin 15 — RESET — Active LOW Reset Output.

This output pin goes LOW whenever V

CC

falls below the reset threshold. This output

pin will remain low typically for 200ms after

V

power-up.

Pin 16 — RESET — Active HIGH Reset

Output. This output pin is open drain and

the inverse of RESET.

Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M

4

1.25V

Reset

Generator

Control

Watchdog

Timer

Reset /

Watchdog

Timebase

Watchdog

Transition

Detector

WDI

BATT ON

LOWLINE

RESET

RESET

PFO

PFI

9

11

8

7

3

1

5

13

12

GND

2

6

16

15

4.65V or

4.40V*

WDO

14

10

4.65V for the SP691A/800L

4.40V for the SP693A/800M

*