SP791EB datasheet(2/6 Pages) SIPEX

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SP791 Evaluation Board Manual

SP791EB/04

BOARD LAYOUT

The SP791 Evaluation Board has been

designed to easily and conveniently provide

access to all pins of the SP791 device under test.

Position the board with the silkscreen lettering

upright (also see drawing on the front page of

this manual) and you will see two vertical rows

of eight pins each, which represent the 16 pins of

the SP791 device starting in the top left with

BATT as pin one. The pin receptacles are raised

female pins which can accommodate easy-

hook connection leads for power and meter

connections, as well as scope probe hooks and

grounds for waveform measurements.

The 16 pin SP791 may be installed in one of 3

locations: U1 for DIP or DIP sockets, U3 for

SOICs or U2 for SOIC sockets. The five input

pins for the SP791 are provided with extra Input

Probe Points for connecting inputs to these pins.

For example pin 11 WDI has nearby pins V

OUT

and GND to connect to for evaluation of WDI

timeout. These female receptacle pins can be

jumpered together with easy-hook connectors

or stripped back solid wire leads. In the case of

inputs SWT or PFI, a resistor or capacitor with

leads may be pushed into the female receptacle

pins to make easy connections. Also, mating

male pins (see List of Materials) may be

soldered to the components and inserted into the

receptacle pins.

USING THE EVALUATION BOARD

Connect the SP791 Evaluation Board to the

power supplies for V

CC and VBATT (see the

section Power Supply Connections following

the table SP791 Pin Assignments). It is good

practice to not switch power on until power

connections are made to the evaluation board.

Evaluating Pin Functions

Pin 1 - V

BATT - Backup-Battery Input.

Connect to external supply, battery or capacitor

and charging circuit.

Pin 2 - V

OUT - Output Supply Voltage. This

function is used to provide power supply

switching of either V

CC or VBATT to an

external device like a CMOS RAM to ensure a

constant supply for the memory. To evaluate

this function, vary the V

CC voltage for a set

BATT voltage until you simulate the following

conditions: V

OUT connects to VCC when VCC

is greater than V

BATT and VCC is above the reset

threshold. When V

CC falls below VBATT and

CC is below the reset threshold, VOUT connects

to V

BATT. Start with VBATT voltage of about 2.8

to 4.0 V and vary V

CC from 0V to 5V to 0V and

observe V

OUT. (Note: a 0.1µF bypass capacitor

(C1) is connected from V

OUT to GND).

Pin 3 - V

CC - Input Supply Voltage - +5V input.

A 0.1

µF bypass capacitor (C2) is connected

from V

to GND.

Pin 4 - GND - Ground reference for all signals.

Pin - 5 - BATT ON - Battery On Output.

Goes high when V

OUT switches to VBATT. Goes

low when V

OUT switches to VCC. Connect the

base of a PNP through a current-limiting resistor

to BATT ON for V

OUT current requirements

greater than 250mA.

Pin 6 - PFO - Power-Fail Output. This is the

output of the power-fail comparator. PFO, goes

low when PFI is less than1.25V. This is an

uncommitted comparator, and has no effect on

any other internal circuitry.

Pin 7 - PFI - Power-Fail Input. This is the

non-inverting input to the power-fail comparator.

When PFI is less than 1.25V, PFO goes low.

Connect PFI to GND or V

OUT when not used.

Connect external divider R1 & R2 to Probe Pins

and connect Unregulated Voltage to UNREG

for Power Fail monitoring.

Pin 8 - SWT - Set Watchdog-Timeout Input.

Connect this input to V

OUT to select the default

1.6 sec watchdog timeout period. Connect a

capacitor (C

SWT ) between the Probe Input Pins

SWT and GND to select another watchdog-

timeout period. Watchdog-timeout period = 2.1

x (capacitor value in nF) ms.

Pin 9 - MR - Manual-Reset Input. This input can

be tied to an external momentary pushbutton

switch, or to a logic gate output. RESET remains

low as long as MR is held Low and for 200ms

after MR returns high. Connect MR to Probe

Pin GND to cause a RESET active low.

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