AX88796 datasheet(40/71 Pages) ASIX

40 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

5.2 The Embedded PHY Registers

The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each

field of the registers. The format for the “FIELD” descriptions is as follows: the first number is the register number, the

second number is the bit position in the register and the name of the instantiated pad is in capital letters. The format for

the “TYPE” descriptions is as follows: R = read, W = write, LH = latch high, NA = not applicable.

ADDRESS

NAME

DESCRIPTION

DEFAULT(Hex Code)

MR0

Control

3000h

MR1

Status

7849h

MR2

PHY Identifier 1

0180h

MR3

PHY Identifier 2

BB10h

MR4

Autonegotiation Advertisement

01E1h

MR5

Autonegotiation Link Partner Ability

0000

MR6

Autonegotiation Expansion

0000

MR7

Next Page Transmit

0000

8 - 15

MR8 -15 (Reserved)

MR16

PCS Control Register

0000

MR17

Autonegotiation (read register A)

0000

MR18

Autonegotiation (read register B)

0000

MR19

Analog Test Register

MR20

User-defined Register

MR21

RXER Counter

0000

22 - 24

MR22 -24 Analog Test Registers

25 - 27

MR25 -27 Analog Test (tuner) Registers

MR28

Device Specific 1

MR29

Device Specific 2

2080

MR30

Device Specific 3

0000

MR31

Quick Status Register

Tab - 14 The Embedded PHY Registers

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