LSM6DS3H datasheet(74/104 Pages) STMICROELECTRONICS

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LSM6DS3H

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DocID028370 Rev 4

9.52

FIFO_STATUS1 (3Ah)

FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in

CTRL3_C (12h) to 0.

Table 137. FIFO_STATUS1 register

Table 138. FIFO_STATUS1 register description

9.53

FIFO_STATUS2 (3Bh)

FIFO status control register (r). For a proper reading of the register it is recommended to set the

BDU bit in CTRL3_C (12h) to 0.

Table 139. FIFO_STATUS2 register

Table 140. FIFO_STATUS2 register description

DIFF_

FIFO_7

DIFF_

FIFO_6

DIFF_

FIFO_5

DIFF_

FIFO_4

DIFF_

FIFO_3

DIFF_

FIFO_2

DIFF_

FIFO_1

DIFF_

FIFO_0

DIFF_FIFO_[7:0]

Number of unread words (16-bit axes) stored in FIFO(1).

1. For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS2 (3Bh)

FTH

FIFO_

OVER_RUN

FIFO_

FULL

FIFO_

EMPTY

DIFF_

FIFO_11

DIFF_

FIFO_10

DIFF_

FIFO_9

DIFF_

FIFO_8

FTH

FIFO watermark status. Default value: 0

(0: FIFO filling is lower than watermark level(1);

1: FIFO filling is equal to or higher than the watermark level)

1. FIFO watermark level is set in FTH_[11:0] in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)

FIFO_OVER_RUN FIFO overrun status. Default value: 0

(0: FIFO is not completely filled; 1: FIFO is completely filled)

FIFO_FULL

FIFO full status. Default value: 0

(0: FIFO is not full; 1: FIFO will be full at the next ODR)

FIFO_EMPTY

FIFO empty bit. Default value: 0

(0: FIFO contains data; 1: FIFO is empty)

DIFF_FIFO_[7:0]

Number of unread words (16-bit axes) stored in FIFO(2).

2. For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS1 (3Ah)

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