STM32F745VG datasheet(21/227 Pages) STMICROELECTRONICS

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STM32F745xx STM32F746xx

Functional overview

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

2.9

Quad-SPI memory interface (QUADSPI)

All devices embed a Quad-SPI memory interface, which is a specialized communication

interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:

•

Direct mode through registers.

•

External flash status register polling mode.

•

Memory mapped mode.

Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.

Code execution is supported.

The opcode and the frame format are fully programmable. Communication can be either in

Single Data Rate or Dual Data Rate.

2.10

LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)

and delivers all signals to interface directly to a broad range of LCD and TFT panels up to

XGA (1024x768) resolution with the following features:

•

2 displays layers with dedicated FIFO (64x32-bit)

•

Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

•

Up to 8 Input color formats selectable per layer

•

Flexible blending between two layers using alpha value (per pixel or constant)

•

Flexible programmable parameters for each layer

•

Color keying (transparency color)

•

Up to 4 programmable interrupt events.

2.11

Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit

blitting, row data copy and pixel format conversion. It supports the following functions:

•

Rectangle filling with a fixed color

•

Rectangle copy

•

Rectangle copy with pixel format conversion

•

Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp

direct color. It embeds dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

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