L6751B datasheet(13/58 Pages) STMICROELECTRONICS

Nome de Peças	L6751B

Descrição Electrónicos	Digitally controlled dual PWM for Intel VR12 and AMD SVI

PDF	58 Pages

Scroll/Zoom	100%

Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

Página de início	http://www.st.com

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13 / 58 page

L6751B

Pin description and connection diagram

Doc ID 024028 Rev 1

13/58

Level sensitive enable pin (3.3 V compatible).

Pull low to disable the device, pull up above the turn-on threshold to enable

the controller.

SVCLK

SVC

Serial clock

ALERT#

V_FIX

Alert (Intel mode).

V_FIX (AMD mode). Pull to 3.3 V to enter V_FIX mode.

SVDATA

SVD

DSerial data

BOOT /

TMAX

Connect a resistor divider to GND/VCC5 in order to define BOOT and

TMAX registers. See Table 10 for details.

VCC5

Main IC power supply.

Operative voltage is 5 V ±5%. Filter with 1

μF MLCC to GND (typ.).

GDC

Gate drive control pin.

Used for efficiency optimization, see Section 9 for details. If not used, it

can be left floating. Always filter with 1

μF MLCC to GND.

n/a

Not internally bonded.

VDRV

Driving voltage for external drivers.

Connect to the selected voltage rail to drive external MOSFET when in

maximum power conditions. IC switches GDC voltage between VDRV and

VCC5 to implement efficiency optimization according to selected strate-

gies.

n/a

Not internally bonded

Table 2.

Pin description (continued)

Pin#

Name

Type

Function

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