SN65DP149 datasheet(13/52 Pages) TI1

13 / 52 page

SN65DP149, SN75DP149

www.ti.com

SLLSEL2A – SEPTEMBER 2015 – REVISED DECEMBER 2015

7.12 DDC and I

2C Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Rise time of both SDA and SCL signals

Vcc = 3.3-V

300

Fall time of both SDA and SCL signals

300

tHIGH

Pulse duration, SCL high

0.6

μs

tLOW

Pulse duration, SCL low

1.3

μs

tSU1

Setup time, SDA to SCL

100

tST, STA

Setup time, SCL to start condition

0.6

μs

tHD,STA

Hold time, start condition to SCL

0.6

μs

tST,STO

Setup time, SCL to stop condition

0.6

μs

t(BUF)

Bus free time between stop and start condition.

1.3

μs

Source-to-sink: 100-kbps pattern;

tPLH1

Propagation delay time, low-to-high-level output Cb(Sink) = 400-pF(1);

360

See Figure 14

tPHL1

Propagation delay time, high-to-low-level output

230

Sink to Source: 100-kbps pattern;

tPLH2

Propagation delay time, low-to-high-level output Cb(Source) = 100-pF(1);

250

See Figure 15

tPHL2

Propagation delay time, high-to-low-level output

200

(1)

Cb = total capacitance of one bus line in pF.

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