SPEAR320S datasheet(26/113 Pages) STMICROELECTRONICS

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Device functions

SPEAr320S

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Doc ID 022508 Rev 2

2.25.1

Reset and clock generator

The reset and clock generator is a fully programmable block that generates all the clocks

necessary to the chip.

The default operating clock frequencies are:

●

Clock @ 333 MHz for the CPU.

●

Clock @ 166 MHz for AHB bus and AHB peripherals.

●

Clock @ 83 MHz for, APB bus and APB peripherals.

●

Clock @ 333 MHz for DDR memory interface.

The default values give the maximum allowed clock frequencies. The clock frequencies are

fully programmable through dedicated registers.

The reset and clock generator consists of 2 main parts:

●

Multiclock generator block

●

3 internal PLLs

The multiclock generator block receives a reference signal (which is usually delivered by the

PLL) and generates all clocks for SPEAr320S IPs according to dedicated programmable

registers.

Each PLL uses an oscillator input of 24 MHz to generate a clock signal at a frequency

corresponding at the highest of the group. This is the reference signal used by the multiclock

generator block to obtain all the other requested clocks for the group. Its main feature is the

electromagnetic interference reduction capability.

You can set up PLL1 and PLL2 in order to modulate the VCO with a triangular wave. The

resulting signal has a spectrum (and power) spread over a small programmable range of

frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic

emissions. This method replaces all the other traditional methods of EMI reduction, such as

filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal

shielding and so on. This offers important cost savings.

2.26

Vectored interrupt controller (VIC)

SPEAr320S integrates a vectored interrupt controller which provides a software interface to

the interrupt system. In any system with an interrupt controller, the software has to

determine the source that requests service and where its service routine is loaded. The VIC

inside SPEAr320S does both of these in hardware. It supplies the starting address, or vector

address, of the service routine corresponding to the highest priority requesting interrupt

source.

As in any ARM9-based system, two levels of interrupts are available:

●

fast interrupt requests (FIQ), for fast, low latency interrupt handling

●

normal interrupt requests (IRQ), for more general interrupts

The interrupt inputs must be level sensitive, active HIGH, and held asserted until the

interrupt service routine clears the interrupt. Edge-triggered interrupts are not compatible.

The interrupt inputs do not have to be synchronous to HCLK. The VIC does not handle

interrupt sources with transient behavior. For example, an interrupt is asserted and then de-

asserted before software can clear the interrupt source. In this case, the CPU acknowledges

the interrupt and obtains the vectored address for the interrupt from the VIC, assuming that

no other interrupt has occurred to overwrite the vectored address. However, when a

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