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M35B32 Folha de dados(PDF) 10 Page - STMicroelectronics |
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M35B32 Folha de dados(HTML) 10 Page - STMicroelectronics |
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10 / 44 page ![]() SPI modes M35B32 10/44 DocID18391 Rev 4 3 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: • CPOL=0, CPHA=0 • CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 3, is the clock polarity when the bus master is in Standby mode and not transferring data: • C remains at 0 for (CPOL=0, CPHA=0) • C remains at 1 for (CPOL=1, CPHA=1) Figure 3. SPI modes supported AI01438B C MSB CPHA D 0 1 CPOL 0 1 Q C MSB |
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