USB3370 datasheet(21/75 Pages) MICROCHIP

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DS00001915B-page 21

USB3370

5.5.2

REFCLK AMPLITUDE

The reference clock should be connected to the REFCLK pin as shown in the application diagrams, Figure 8-1. The

REFCLK

pin is designed to be driven with a square wave from 0V to VDDIO, but can be driven with a square wave from

0V to as high as 3.6V. The USB3370 uses only the positive edge of the REFCLK.

If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the

REFCLK

pin. If using an analog clock the DC bias should be set at the mid-point of the VDD18 supply using a bias

circuit as shown in Figure 5-4. The amplitude must be greater than 300mV peak to peak. The component values pro-

vided in Figure 5-4 are for example only. The actual values should be selected to satisfy system requirements.

The REFCLK amplitude must comply with the signal amplitudes shown in Table 4-4 and the duty cycle in Table 4-2.

5.5.3

REFCLK JITTER

The USB3370 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of

less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Clock Input

Mode or ULPI Clock Output Mode, the USB3370 High Speed eye diagram may be degraded.

The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table 4-2.

FIGURE 5-3:

CONFIGURING THE USB3370 FOR ULPI CLOCK OUTPUT MODE

FIGURE 5-4:

EXAMPLE OF CIRCUIT USED TO SHIFT A REFERENCE CLOCK COMMON-

MODE VOLTAGE LEVEL

CLKOUT

REFCLK

PHY

From PLL

Clock

Source

To PLL

Link

ULPI Clk In

Clock

0.1uF

1.8V Supply

To REFCLK pin

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