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ADP5054ACPZ-R7 Folha de dados(PDF) 26 Page - Analog Devices

Nome de Peças ADP5054ACPZ-R7
Descrição Electrónicos  Quad Buck Regulator Integrated Power Solution
PDF  31 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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ADP5054ACPZ-R7 Folha de dados(HTML) 26 Page - Analog Devices

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ADP5054
Data Sheet
Rev. B | Page 26 of 31
SELECTING THE OUTPUT CAPACITOR
The output capacitor must meet the output voltage ripple and
load transient requirements. To meet the output voltage ripple
requirement, use the following equations to calculate the ESR
and capacitance:
OUT_RIPPLE
SW
L
OUT_RIPPLE
V
f
I
C
×
×
=
8
L
OUT_RIPPLE
ESR
I
V
R
=
The calculated capacitance, COUT_RIPPLE, is 20.8 µF, and the
calculated ESR, RESR, is 10 mΩ.
To meet the ±5% overshoot and undershoot requirements,
use the following equations to calculate the capacitance:
(
)
UV
OUT
OUT
IN
STEP
UV
UV
OUT
V
V
V
L
I
K
C
_
2
_
2
×
×
×
×
=
(
)
2
2
2
_
OUT
OUT_OV
OUT
STEP
OV
OV
OUT
V
V
V
L
I
K
C
+
×
×
=
For estimation purposes, use KOV = KUV = 2; therefore,
COUT_OV = 117 µF and COUT_UV = 13.3 µF.
The ESR of the output capacitor must be less than 13.3 mΩ,
and the output capacitance must be greater than 117 µF. It is
recommended that three ceramic capacitors be used (47 µF,
X5R, 6.3 V), such as the GRM21BR60J476ME15 from Murata
with an ESR of 2 mΩ.
SELECTING THE LOW-SIDE MOSFET
A low RDS(ON) N-channel MOSFET must be selected for high
efficiency solutions. The MOSFET breakdown voltage must be
greater than 1.2 × VIN, and the drain current must be greater
than 1.2 × ILIMIT.
It is recommended that a 20 V, dual N-channel MOSFET (such
as the Si4204DY from Vishay) be used for both Channel 1 and
Channel 2. The RDS(ON) of the Si4204DY at a 4.5 V driver voltage
is 6 mΩ, and the total gate charge is 14.5 nC.
DESIGNING THE COMPENSATION NETWORK
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this example, fSW is set to 600 kHz;
therefore, fC is set to 60 kHz.
For the 1.2 V output rail, the 47 µF ceramic output capacitor has
a derated value of 32 µF.
77
.
5
A/V
20
μs
470
V
8
.
0
kHz
60
μF
32
3
V
2
.
1
2
=
×
×
×
×
×
×
π
×
=
C
R
(
)
nF
01
.
5
77
.
5
μF
32
3
Ω
001
.
0
Ω
3
.
0
=
×
×
+
=
C
C
pF
6
.
16
77
.
5
μF
32
3
Ω
001
.
0
=
×
×
=
CP
C
Choose standard components: RC = 5.6 kΩ and CC = 4.7 nF.
CCP is optional.
Figure 40 shows the bode plot for the 1.2 V output rail. The
cross frequency is 64 kHz, and the phase margin is 65°.
Figure 41 shows the load transient waveform.
–120
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
–120
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
1k
10k
100k
1M
FREQUENCY (Hz)
CROSS FREQUENCY: 64kHz
PHASE MARGIN: 65°
Figure 40. Bode Plot for 1.2 V Output
Figure 41. 0.8 A to 3.2 A Load Transient Waveform for 1.2 V Output
SELECTING THE SOFT START TIME
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current.
The CFG12 pin can be used to program a soft start time of 2 ms
or 16 ms and can also be used to configure parallel operation of
Channel 1 and Channel 2. For more information, see the Soft
Start section and Table 8.
SELECTING THE INPUT CAPACITOR
For the input capacitor, select a ceramic capacitor with a
minimum value of 10 µF; place the input capacitor close to the
PVINx pin. In this example, one ceramic capacitor of 10 µF,
X5R, 25 V is recommended.



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