AS1345C datasheet(22/29 Pages) AMSCO

22 / 29 page

AS1345 – 22

ams Datasheet, Confidential: 2013-Nov [1-51]

De tail ed De sc rip t ion

PCB Layout

Carefully printed circuit layout is important for minimizing

ground bounce and noise. Keep the GND pin and ground pads

for the input and output capacitors as close together as

possible. Keep the connection to LX as short as possible. Locate

the feedback resistors as close as possible to the FB pin and

keep the feedback traces routed away from noisy areas such as

LX.

EMI and overall performance quality are affected by the PCB

layout. The high speed operation of the AS1345 demands

careful attention to board layout. Stated performance will be

difficult to achieve with careless layout. Figure 25 identifies the

high current paths during an operation cycle involving the

switching of the N-channel and P-channel internal switches.

The current paths between SWIN, VIN, C1, C2, C4, L1, D1 and

GND should be short and wide for lowest intrinsic resistive loss

and lowest stray inductance.

A large ground pin copper area will help to lower the chip

temperature. A multilayer board with a separate ground plane

is ideal, but not absolutely necessary.

Figure 25:

AS1345 - Inductor Current Paths

AS1345

PDRV

NDRV

ILIM

RLOAD

SWIN

VDD

SWOUT

GND

VBAT

VOUT

Inductor Current Path NMOS-OFF, D1-ON

Load Current Path NMOS-OFF, D1-OFF

Inductor Current Path NMOS-ON, D1-OFF

AS1345C Folha de dados(PDF) 22 Page - ams AG