MT91L60AS datasheet(2/32 Pages) MITEL

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MT91L60/61

Advance Information

Figure 2 - Pin Connections

Pin Description

Pin #

20 Pin

24 Pin

Name

Description

VBias

Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external

ampliﬁers. Connect 0.1

µF capacitor to V

SSA.

VRef

Reference Voltage for Codec (Output). Used internally. Nominally [Vdd/2 - 1.1]

volts. Connect 0.1

µF capacitor to V

SSA.

PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).

Internal Connection. Tie externally to VSSD for normal operation.

µ/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs

the companding law used by the ﬁlter/Codec;

µ-Law when tied to V

SSD and A-Law

when tied to VDD. Logically OR’ed with A/µ register bit.

IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt

output signalling valid access to the D-Channel registers in ST-BUS mode.

VSSD

Digital Ground. Nominally 0 volts.

Chip Select (Input).

This input signal is used to select the device for microport

data transfers. Active low. CMOS level compatible.

SCLK

Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level

compatible.

DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/

National mode of operation, this pin becomes the data transmit pin only and data

receive is performed on the DATA 2 pin. Input CMOS level compatible.

DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for

data receive. In Intel mode, serial data transmit and receive are performed on the

DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.

Dout

Data Output. A high impedance three-state digital output for 8 bit wide channel

data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent

with the rising edge of the bit clock during the timeslot deﬁned by STB, or according

to standard ST-BUS timing.

Din

Data Input. A digital input for 8 bit wide channel data received from the Layer 1

transceiver. Data is sampled on the falling edge of the bit clock during the timeslot

deﬁned by STB, or according to standard ST-BUS timing. Input level is CMOS

compatible.

M -

M +

VBias

VRef

VSSD

SCLK

DATA1

DATA2

Din

Dout

VSSA

HSPKR +

HSPKR -

VDD

PWRST

µ/IRQ

STB/F0i

CLOCKin

M -

M +

VBias

VRef

VSSD

SCLK

DATA1

DATA2

Din

Dout

VSSA

HSPKR +

HSPKR -

VDD

PWRST

µ/IRQ

STB/F0i

CLOCKin

20 PIN SOIC/SSOP

24 PIN PDIP

M -

M +

VBias

VRef

VSSD

SCLK

DATA1

DATA2

Din

Dout

VSSA

HSPKR +

HSPKR -

VDD

PWRST

µ/IRQ

STB/F0i

STBd/FOod

CLOCKin

24 PIN PDIP/SOIC/SSOP

MT91L60AS/AN

MT91L60AE

MT91L61AE/AS/AN

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