PHT

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Vishay Sfernice

Revision: 14-Jan-15

3

Document Number: 53050

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

POWER DERATING CURVE

DIMENSIONS in millimeters (inches)

SUGGESTED LAND PATTERN (TO IPC-7351A)

Caution:

Performances obtained with following mounting conditions:

PCB: polyimide

Solder paste: PbSnAg (93.5/5/1.5)

CASE SIZE

AB

C

D/E

MAX. TOL.

+0.152 (+0.006)

MIN. TOL.

-0.152 (-0.006)

MAX. TOL.

+0.127 (+0.005)

MIN. TOL.

-0.127 (-0.005)

NOMINAL

NOMINAL

NOMINAL

TOLERANCE

0402

1.00 (0.039)

0.60 (0.024)

Termination N:

0.5 (0.02)

± 0.127 (0.005)

Termination G:

0.4 (0.016)

± 0.051 (0.002)

0.25 (0.010)

0.1 (0.004)

0603

1.52 (0.060)

0.85 (0.033)

0.38 (0.015)

0.13 (0.005)

0805

1.91 (0.075)

1.27 (0.050)

1206

3.06 (0.120)

1.60 (0.063)

0.40 (0.016)

2010

5.08 (0.200)

2.54 (0.100)

0.48 (0.019)

CHIP SIZE

DIMENSIONS (in millimeter)

0402

1.55

0.15

0.73

0603

2.37

0.35

0.98

0805

2.76

0.74

1.40

1206

3.91

1.85

1.73

2010

5.93

3.71

2.67

Ambient Temperature in °C

350

300

250

200

150

100

50

0

50

200

100

250

0150

A

D

D

C

E

E

B

G

min.

Z

max.

X

max.