ACE9030MSLASHIWSLASHFP2N datasheet(31/39 Pages) MITEL

31 / 39 page

ACE9030

Increment

Accumulator

Division

( = NF )

value

Ratio

...previous values

TOT

& overflows

TOT + 1

TOT

& overflows

TOT + 1

TOT

& overflows

TOT + 1

TOT

& overflows

TOT + 1

and so on...

and in this case the phase error increases in the opposite

direction each cycle by:

This phase error gives an unwanted correction pulse on

the Ø

UP output, as the VCO frequency is too low for the division

ratio in use.

Any phase can be considered to be the locked condition

so to simplify later calculations the phase given by a

÷ (NTOT

+ 1) cycle which leaves 000 in the accumulator will be chosen

as the locked state and compensation will be added to achieve

this. Only unwanted Ø

DOWN outputs then need to be removed

by cancellation and also that the total phase error in any cycle,

based on formula (2), is given by replacing F, the fraction

required, by the current sum of fractions, which is the value of

the accumulator ACC divided by the modulus in use. This

replacement is clearly valid if the state of the accumulator is

considered when starting from a zero value and then adding

the fractional count each cycle until an overflow is reached;

when starting from a non-zero value there is some residual

phase error from the overflow state so the accumulator still

gives the correct phase error. Thus the phase error needing

correction on the loop filter is:

This error could be cancelled by a phase shift on the

comparison clock from the reference divider but this is very

difficult in practice so the method used in ACE9030 is to add

an extra charge pump to the loop filter to directly cancel the

pulse given by the normal charge pump due to this phase

error. The current given by the proportional charge pump is

Iprop(0) in normal mode or Iprop(1) in speed-up mode so

taking normal mode first the charge that must be cancelled is:

This formula could be used as it stands but the circuit can

be simplified if it is recalled that Iprop(0) depends on the CN

value so that loop dynamics are kept constant over a wide

range of frequencies by changing CN in proportion to the total

division ratio N

TOT. In those systems where CN is held constant

the synthesiser is in effect considered to be operating over a

narrow frequency band so N

TOT

can also be considered

constant and the following calculations still apply. The value of

Iprop(0) is set by a DAC in ACE9030 from the reference

current Ibo so that:

and the value of CN tracks N

TOT with a scaling factor SF such

that:

putting both of these equations into formula (5) gives the

charge to be cancelled as:

NF is the fraction set in Word A or A2

MOD is the modulus, 5 or 8

disturbed by the variations in division ratio but there is still

some frequency modulation given by the Fractional-N opera-

tion. The simplest way to remove this ripple on the synthesiser

is to use a lower bandwidth loop filter but this also removes all

of the advantage of fast channel change when using Frac-

tional-N, so the method used in ACE9030 is to calculate the

waveform of the ripple and then inject a compensation signal

onto the loop filter.

Fractional-N Compensation

If the Fractional-N system is operating correctly the

synthesiser sets the VCO frequency so that:

where F is the fraction given by:

The total division alternates between N

TOT and NTOT + 1 so

the frequency seen at the phase comparator will also alter-

nate. This divided signal f

FRACN is compared with the uniform

comparison frequency f

COMP and will give a phase error due to

the different periods. There will also be some phase error due

to leakage on the loop filter, leading to some correction pulses

on the charge pumps to maintain lock, but these will be very

small in a well designed synthesiser once the loop is locked,

so can be ignored here. For each

÷ (N

TOT) cycle:

and so the phase error increases each cycle by:

This phase error gives an unwanted correction pulse on

the Ø

DOWN output as the VCO frequency is too high for the

division ratio in use. The phase error increases as

÷ N

TOT

cycles follow each other until eventually the accumulator

overflows and causes a

÷ (N

TOT + 1) cycle.

For each

÷ (N

TOT + 1) cycle:

Table 7

x (fCOMP Period) .... (2)

NTOT

fVCO = fCOMP x (NTOT + F) .... (1)

MOD

F =

fFRANC = fCOMP x

NTOT + 1

NTOT + F

fFRANC = fCOMP x

fCOMP x 1+

NTOT

NTOT + F

NTOT

NTOT + F

(

)

x (fCOMP Period) .... (3)

(NTOT + 1)

(F - 1)

Phase error =

x (fCOMP Period) .... (4)

NTOT x MOD

ACC

Iprop (0) = CN x Ibo .... (6)

CN = SF x NTOT

Charge =

x (fCOMP Period) x Ibo .... (7)

MOD

ACC x SF

x (fCOMP Period) x Iprop (0) .... (5)

NTOT x MOD

ACC

ACE9030M/IW/FP2N Folha de dados(PDF) 31 Page - Mitel Networks Corporation

ACE9030M/IW/FP2N Folha de dados(HTML) 31 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Folha de dados Download

Ligação URL