ASM1232LP, ASM1232LPS

http://onsemi.com

5

Detailed Description

The ASM1232LP/LPS monitors the microprocessor or

micro controller power supply and generates reset signal,

both active HIGH and Active LOW, that halt processor

operation whenever the power supply voltage levels are

outside a predetermined tolerance.

RESET and RESET outputs

RESET is an active HIGH signal developed by a CMOS

push−pull output stage and is the logical opposite to RESET.

RESET is an active LOW signal. It is developed with an

open drain driver. A pull up resistor of typical value 10 k

W

to 50 k

W is required to connect with the output.

Trip Point Tolerance Selection

below 5 V without asserting a reset. With TOL connected to

falls below 4.5 V. RESET and RESET become active when

RESET and RESET remain active for a minimum time

reset threshold RESET stays LOW and is guaranteed to be

Tolerance Select

Tolerance

TRIP Point Voltage (V)

Min

Nom

Max

10%

4.25

4.37

4.49

TOL = GND

5%

4.5

4.62

4.74

Figure 3. Timing Diagram: Power Up

Figure 4. Timing Diagram: Power Down