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MT9M034 Folha de dados(PDF) 39 Page - ON Semiconductor |
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MT9M034 Folha de dados(HTML) 39 Page - ON Semiconductor |
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39 / 56 page ![]() MT9M034_DS Rev. G Pub. 4/15 EN 39 ©Semiconductor Components Industries, LLC,2015. MT9M034: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Single READ from Random Location This sequence (Figure 18) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the READ by generating a no-acknowl- edge bit followed by a stop condition. Figure 18 shows how the internal register address maintained by the MT9M034 is loaded and incremented as the sequence proceeds. Figure 18: Single READ from Random Location Single READ from Current Location This sequence (Figure 19) performs a read using the current value of the MT9M034 internal register address. The master terminates the READ by generating a no-acknowl- edge bit followed by a stop condition. The figure shows two independent READ sequences. Figure 19: Single READ from Current Location Sequential READ, Start from Random Location This sequence (Figure 20) starts in the same way as the single READ from random loca- tion (Figure 18). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until “L” bytes have been read. Figure 20: Sequential READ, Start from Random Location S = start condition P = stop condition Sr = restart condition A = acknowledge A = no-acknowledge slave to master master to slave Slave Address 0 S A Reg Address[15:8] A Reg Address[7:0] Slave Address A A 1 Sr Read Data P Previous Reg Address, N Reg Address, M M+1 A Slave Address 1 S A Read Data Slave Address A 1 S P Read Data P Previous Reg Address, N Reg Address, N+1 N+2 A A Slave Address 0 S Sr A Reg Address[15:8] Read Data Read Data A Reg Address[7:0] A Read Data Slave Address Previous Reg Address, N Reg Address, M M+1 M+2 M+1 M+3 A 1 Read Data Read Data M+L-2 M+L-1 M+L A P A A A A |
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