ML6460

16

Figure 8a. Pixel Synchronization. For External Mode, Active Edge at Beginning of Horizontal Blanking.

(HRESET_MODE = 0, SENSE_HSYNC = 1, BL = Blanked Pixel)

Figure 8. Pixel Synchronization. For External Mode, Active Edge at Beginning of Horizontal Blanking.

(HRESET_MODE = 0, SENSE_HSYNC = 0, BL = Blanked Pixel)

CLK

HSYNC

(input)

YCrCb

BL

BL

A

B

C

D

E

F

GH

Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0)

Beginning

of Horizontal

Blanking

P Clock Cycles

(0,0)

CB0

Y0

CR0

Y1

CB2

Y2

CR2

Y3

(0,1)

BL

CB0

Y0

CR0

Y1

CB2

Y2

CR2

(1,0)

BL

BL

CB0

Y0

CR0

Y1

CB2

Y2

(1,1)

BL

BL

BL

CB0

Y0

CR0

Y1

CB2

A

B

C

D

E

F

G

H

Bit

Value (SEL_HSYNC1, SEL_HSYNC0)

# of Clock Cycles, P

if SELCCIR = 1

if SELCCIR = 0

244

220

252

220

If ANALOG_HBLANK = 0

If ANALOG_HBLANK = 1

CLK

HSYNC

(input)

YCrCb

BL

BL

A

B

C

D

E

F

GH

Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0)

Beginning

of Horizontal

Blanking

P Clock Cycles

(0,0)

CB0

Y0

CR0

Y1

CB2

Y2

CR2

Y3

(0,1)

BL

CB0

Y0

CR0

Y1

CB2

Y2

CR2

(1,0)

BL

BL

CB0

Y0

CR0

Y1

CB2

Y2

(1,1)

BL

BL

BL

CB0

Y0

CR0

Y1

CB2

A

B

C

D

E

F

G

H

Bit

Value (SEL_HSYNC1, SEL_HSYNC0)

# of Clock Cycles, P

if SELCCIR = 1

if SELCCIR = 0

244

220

252

220

If ANALOG_HBLANK = 0

If ANALOG_HBLANK = 1