ML2653CQ datasheet(16/23 Pages) MICRO-LINEAR

16 / 23 page

ML2652/ML2653

controller via the controller interface. In addition, the

receive section detects and automatically corrects for

reverse polarity, detects link pulses, detects start of idle

pulses, and implements an intelligent receive squelch

algorithm. The receive section can successfully lock onto

an incoming data that contains ±18ns of jitter in less than

1.6µs.

The miscellaneous functions are the controller interface,

single pin crystal oscillator, AUI, loopback modes, test

mode, and powerdown mode. The ML2653 has no AUI

interface output.

The following text describes each of these blocks and

functions in more detail. Refer to the block diagram.

TRANSMISSION

The transmit data (NRZ) is first clocked into the device

through the controller interface. The device can be

digitally programmed to accommodate any one of four

standard Ethernet controllers as described in Controller

section.

FUNCTIONAL DESCRIPTION

GENERAL

The ML2652 and ML2653 are composed of a transmitter

section, receive section and some miscellaneous

functions.

The transmit section consists of the manchester encoder,

AUI, jabber detect, link pulse generator, start of idle (SOI)

pulse generator, waveform generator, and line driver. The

purpose of the transmit section is to take data from the

controller, encode it, and transmit it over either the AUI or

twisted pair interface. In addition, the transmit section

generates link pulses, start of idle pulses, and checks for

jabber condition. The transmitter keeps the data jitter to a

maximum of ±8.0ns, and the maximum delay through the

transmission section is less than 2 bits, or 200ns.

The receive section consists of the manchester decoder,

collision detect, AUI, receive LPF, receive comparators,

receive squelch, automatic polarity correct, start of idle

(SOI) detect, and link pulse detect. The purpose of the

receive section is to take data from either the twisted pair

cable or AUI, decode it, then send the data to the

APPLICATION CIRCUIT — ML2653

TxC

TxD

TxE

COL

RxC

RxD

RxE

LPBK

CS0

CS1

CS2

RSL

XMT/RCV

LTP

RPOL

VCC

CLK GND GND RTX

Tx+

Tx–

Rx+

Rx–

0.1µF

+5V

200

Ω

+5V

200

Ω

10K

RJ45

2:1

1:1

ETHERNET

CONTROLLER

(SEE TABLE 1)

SEEQ 8003

SEEQ 8005

NSC DP8390

AMD AM7990

INTEL 82586

INTEL 82596

+5V

ML2653

+5V

510

Ω

510

Ω

5.1K

Figure 13

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