LM3524DM datasheet(9/29 Pages) TI

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LM2524D, LM3524D

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SNVS766E – JUNE 2009 – REVISED MAY 2013

Functional Description

Internal Voltage Regulator

The LM3524D has an on-chip 5V, 50 mA, short circuit protected voltage regulator. This voltage regulator

provides a supply for all internal circuitry of the device and can be used as an external reference.

For input voltages of less than 8V the 5V output should be shorted to pin 15, VIN, which disables the 5V

regulator. With these pins shorted the input voltage must be limited to a maximum of 6V. If input voltages of

6V–8V are to be used, a pre-regulator, as shown in Figure 11, must be added.

*Minimum CO of 10 μF required for stability.

Figure 11.

Oscillator

The LM3524D provides a stable on-board oscillator. Its frequency is set by an external resistor, RT and capacitor,

CT. A graph of RT, CT vs oscillator frequency is shown is Figure 12. The oscillator's output provides the signals

for triggering an internal flip-flop, which directs the PWM information to the outputs, and a blanking pulse to turn

off both outputs during transitions to ensure that cross conduction does not occur. The width of the blanking

pulse, or dead time, is controlled by the value of CT, as shown in Figure 13. The recommended values of RT are

1.8 k

Ω to 100 kΩ, and for CT, 0.001 μF to 0.1 μF.

If two or more LM3524D's must be synchronized together, the easiest method is to interconnect all pin 3

terminals, tie all pin 7's (together) to a single CT, and leave all pin 6's open except one which is connected to a

single RT. This method works well unless the LM3524D's are more than 6″ apart.

A second synchronization method is appropriate for any circuit layout. One LM3524D, designated as master,

must have its RTCT set for the correct period. The other slave LM3524D(s) should each have an RTCT set for a

10% longer period. All pin 3's must then be interconnected to allow the master to properly reset the slave units.

The oscillator may be synchronized to an external clock source by setting the internal free-running oscillator

frequency 10% slower than the external clock and driving pin 3 with a pulse train (approx. 3V) from the clock.

Pulse width should be greater than 50 ns to insure full synchronization.

Figure 12.

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