PIC16F870SLASHSP datasheet(97/156 Pages) MICROCHIP

97 / 156 page

Preliminary

DS30569A-page 97

PIC16F870/871

FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

ADCON1

870

871

0--- 0000

u--- uuuu

EEDATA

870

871

0--- 0000

u--- uuuu

EEADR

870

871

xxxx xxxx

uuuu uuuu

EEDATH

870

871

xxxx xxxx

uuuu uuuu

EEADRH

870

871

xxxx xxxx

uuuu uuuu

EECON1

870

871

x--- x000

u--- u000

u--- uuuu

EECON2

870

871

---- ----

TABLE 11-6:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

Wake-up via WDT or

Interrupt

Legend: u = unchanged,

= unknown,

= unimplemented bit, read as ’0’, q = value depends

on condition, r = reserved maintain clear.

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the inter-

rupt vector (0004h).

3: See Table 11-5 for reset value for specific condition.

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

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