TLV320AIC3206_15 datasheet(7/51 Pages) TI

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TLV320AIC3206

www.ti.com

SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014

8.2 Handling Ratings

MIN

MAX

UNIT

Tstg

Storage temperature range

–55

125

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

–2

pins(1)

V(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

–750

750

JESD22-C101, all pins(2)

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

AVDD

Referenced to AVss(1)

1.5

1.8

1.95

IOVDD

Referenced to IOVss(1)

1.1

3.6

Power Supply Voltage Range

Vsys

Referenced to DVss(1)

1.5

1.8

5.5

DVdd(2)

Referenced to DVss(1)

1.26

1.8

1.95

DVDD_CP

Power Supply Voltage Range

Referenced to DVss(1)

1.26

1.8

1.95

Referenced

Ground-centered config

1.5

1.8

1.95

DRVDD_HP

to AVss(1)

Unipolar config

1.5

3.6

Clock divider uses fractional divide

(D > 0), P = 1, DVdd ≥ 1.65V (See table in

MHz

SLAA463, Maximum TLV320AIC3206 Clock

Frequencies)

PLL Input Frequency

Clock divider uses integer divide

(D = 0), P = 1, DVdd ≥ 1.65V (See table in

0.512

MHz

SLAA463, Maximum TLV320AIC3206 Clock

Frequencies)

MCLK; Master Clock Frequency; DVdd ≥ 1.65V

MHz

MCLK

Master Clock Frequency

MCLK; Master Clock Frequency; DVdd ≥ 1.26V

SCL

SCL Clock Frequency

400

kHz

0.75 or

CM = 0.75 V

0.530

AVDD - Vpeak

Audio input max ac signal swing

0.75(3)

(IN1_L, IN1_R, IN2_L, IN2_R,

0.9 or

IN3_L, IN3_R)

CM = 0.9 V

0.707

AVDD - Vpeak

0.9(3)

LOL, LOR

Stereo line output load

0.6

Ω

resistance

Stereo headphone output load

Single-ended configuration

14.4

Ω

resistance

HPL, HPR

Headphone output load

Differential configuration

24.4

Ω

resistance

CLout

Digital output load capacitance

TOPR

Operating Temperature Range

–40

°C

(1)

All grounds on board are tied together; they must not differ in voltage by more than 0.2V max, for any combination of ground signals.

(2)

At DVdd values lower than 1.65V, the PLL does not function. Please see table in SLAA463, Maximum TLV320AIC3206 Clock

Frequencies for details on maximum clock frequencies.

(3)

Whichever is smaller

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