Figure 11. 3-Byte SPI Daisy-Chain Data Register Read Example

CS

SI

SENSEn

SCK

SPI Mode 0

12

3

4

5

67

High Z

8

12

3

4

5

67

8

12

3

4

5

67

Byte 2

Byte 3

HOLT INTEGRATED CIRCUITS

8

Figure 13. Padded 2-Byte Configuration Register Write Example

SEL

SO

Byte 1

SI16

SI15 SI14 SI13 SI12 SI11 SI10

SI9

SI8

SI7

SI6

SI5

SI4

SI3

SI1

SI2

VALID

DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 SI16

SI14 SI13 SI12 SI11 SI10

SI9

SI8

SI7

SI6

SI5

SI4

SI3

SI1

SI2

SI15

High Z

SI data is shifted out of SO after 8 SCK cycles

Sensor state is latched into Data Register on falling edge of CS

8

FUNCTIONAL DESCRIPTION (cont.)

HI-8428-R

CR9

High Z

High Z

CS

SO

SI

SCK (SPI Mode 0)

Figure 12. Nine-bit Configuration Register Write Example

SEL

CR8

CR7

CR6

CR4

CR3

CR2

CR1

NCD9

New Configuration Register data (NCD9-1) is loaded into Configuration Register on

rising edge

CS

CR5

NCD9

NCD8

NCD7

NCD6

NCD4

NCD3

NCD2

NCD1

NCD5

NCDn = New Configuration Register bits to be written to CR

CRn = Old Configuration Register bits read from CR prior to CR write

CS

SI

SCK

SPI Mode 0

12

3

4

5

67

High Z

8

12

3

4

5

67

8

Byte 2

SEL

SO

Byte 1

X

X

X

XXX

X

NCD

9

CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2

X

High Z

XX

XX

X

X

CR1

NCD

8

NCD

7

NCD

6

NCD

5

NCD

4

NCD

3

NCD

2

NCD

1

NCD

9

New Configuration Register data (NCD9-1) is loaded into Configuration Register on

rising edge

CS

NCDn = New Configuration Register bits to be written to CR

CRn = Old Configuration Register bits read from CR prior to CR write

X = Don’t care padding bits