UCD3138A64PFCR datasheet(11/80 Pages) TI

11 / 80 page

UCD3138128, UCD3138A64

www.ti.com

SLUSBZ8A – JUNE 2014 – REVISED SEPTEMBER 2014

Electrical Characteristics (continued)

V33A = V33D = V33DIO = 3.3V; 1

μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Internal signal warning of brownout

Brownout

2.9

conditions

TEMPERATURE SENSOR(2)

VTEMP

Voltage range of sensor

1.46

2.44

Voltage resolution

Volts/°C

6.3

mV/ºC

Temperature resolution

Degree C per bit

0.0969

ºC/LSB

Accuracy(2)(7)

-40°C to 125°C

–10

±5

ºC

Temperature range

-40°C to 125°C

–40

125

ºC

ITEMP

Current draw of sensor when active

μA

VAMB

Ambient temperature

Trimmed 25°C reading

1.87

ANALOG COMPARATOR

DAC

Reference DAC Range

2.5

Reference Voltage

2.478

2.5

2.513

Bits

bits

INL(2)

–0.42

0.21

LSB

DNL(2)

0.06

0.12

LSB

Offset

–5.5

19.5

Reference DAC buffered output load(8)

0.5

Buffer offset (-0.5 mA)

8.3

Buffer offset (1.0 mA)

RTC INTERFACE

fRTC

RTC external input frequency

MHz

(7)

Ambient temperature offset value from the TEMPSENCTRL register should be used to meet accuracy.

(8)

Available from reference DACs for comparators D, E, F and G.

8.6 Timing Characteristics

V33A = V33D = V33DIO = 3.3V; 1

μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

EADC DAC

Settling Time

From 10% to 90%

250

ADC12

ADC single sample conversion time(1)

ADC_SAMPLING_SEL= 6 or 0

3.9

μs

SYSTEM PERFORMANCE

Total time is: TWD x

TWD

Watchdog time out resolution

10.5

13.3

(WDCTRL.PERIOD+1)

Time to disable DPWM output based on

High level on FAULT pin

active FAULT pin signal

Flash Read

MCLKs

tDelay

Digital filter delay(2)

(1 clock = 32ns)

MCLKs

Retention period of flash content (data

TJ = 25°C

100

years

retention and program)

Program time to erase one page or block in

data flash or program flash

Program time to write one word in program

µs

flash

(1)

Characterized by design and not production tested.

(2)

Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which

has no variation associated with it, must be accounted for when calculating the system dynamic response.

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