UCD3138128PFCR datasheet(10/80 Pages) TI

10 / 80 page

UCD3138128, UCD3138A64

SLUSBZ8A – JUNE 2014 – REVISED SEPTEMBER 2014

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Electrical Characteristics (continued)

V33A = V33D = V33DIO = 3.3V; 1

μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Gain

See Figure 10

V/V

Minimum output voltage

EADC DAC

DAC range

1.6

VREF DAC reference resolution

10 bit, No dithering enabled

1.56

VREF DAC reference resolution

With 4 bit dithering enabled

97.6

μV

INL

–1.5

1.5

LSB

DNL

–1.0

2.1

LSB

DAC reference voltage

1.58

1.61

ADC12

IBIAS

Bias current for PMBus address pins

9.5

10.5

μA

Measurement range for voltage monitoring

2.5

Internal ADC reference voltage

–40°C to 125°C

2.475

2.500

2.53

–40°C to 25°C

–0.7

Change in Internal ADC reference from

25°C reference voltage(1)

25°C to 125°C

-6

ADC12 INL integral nonlinearity(2)

-7.5/+2.9

LSB

ADC12 DNL differential nonlinearity(2)

–0.7/+3.2

LSB

ADC_SAMPLING_SEL = 6 for all

ADC12 data, 25 °C to 125 °C

ADC Zero Scale Error

–7

±5

ADC Full Scale Error

–35

±20

Input bias

2.5 V applied to pin

200

Input leakage resistance(2)

ADC_SAMPLING_SEL= 6 or 0

Ω

Input Capacitance(2)

DIGITAL INPUTS/OUTPUTS(3)(4)

DGND

VOL

Low-level output voltage(5)

IOH = 4 mA, V33DIO = 3 V

+ 0.25

V33DIO

VOH

High-level output voltage (5)

IOH = –4 mA, V33DIO = 3 V

– 0.6

VIH

High-level input voltage

V33DIO = 3 V

2.1

VIL

Low-level input voltage

V33DIO = 3 V

1.1

IOH

Output sinking current

IOL

Output sourcing current

–4

SYSTEM PERFORMANCE

Processor master clock (MCLK)

31.25

MHz

tDelay

Digital filter delay(6)

(1 clock = 32ns)

MCLKs

f(PCLK)

Internal oscillator frequency

240

250

260

MHz

Current share current source (See

ISHARE

238

259

μA

Figure 28)

RSHARE

Current share resistor (See Figure 28)

9.7

10.3

POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3)

VGH

Voltage good High

2.7

VGL

Voltage good Low

2.5

Vres

Voltage at which IReset signal is valid(2)

0.8

(2)

Characterized by design and not production tested.

(3)

DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.

(4)

On the 40 pin package V33DIO is connected to V33D internally.

(5)

The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop

specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.

(6)

Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which

has no variation associated with it, must be accounted for when calculating the system dynamic response.

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