UCD3138128PFC datasheet(17/80 Pages) TI

17 / 80 page

UCD3138128, UCD3138A64

www.ti.com

SLUSBZ8A – JUNE 2014 – REVISED SEPTEMBER 2014

9 Detailed Description

9.1 Overview

9.1.1 ARM Processor

The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit

microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where

two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The

Thumb instructions allow for higher code density equivalent to a 16-bit microprocessor, with the performance of

the 32-bit microprocessor.

The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in

the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter.

9.1.2 Memory

The UCD3138x (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the

memory modules. All of the memory module addresses are sequentially aligned along the same address range.

This applies to program flash, data flash, ROM and all other peripherals.

Within the UCD3138 family architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware

startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM is

executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the

ROM code branches to the main FLASH-program execution. If there is no valid program, the device waits for a

program download through the PMBus.

The UCD3138 family also supports customization of the boot program by allowing an alternative boot routine to

be executed from program FLASH. This feature enables assignment of a unique address to each device;

therefore, enabling firmware reprogramming even when several devices are connected on the same

communication bus.

There are three separate flash memory areas present inside the device. There are 2-32 kB program flash blocks

and 1-2 kB data flash area. The 32 kB program areas are organized as 8 k x 32 bit memory blocks and are

intended to be for the firmware programs. The blocks are configured with page erase capability for erasing blocks

as small as 1 kB per page, or with a mass erase for erasing the entire 32 kB array. The flash endurance is

specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data flash array is

organized as a 512 x 32 bit memory (32 byte page size). The data flash is intended for firmware data value

storage and data logging. Thus, the Data flash is specified as a high endurance memory of 20 k cycles with

embedded error correction code (ECC).

For run time data storage and scratchpad memory, a 8 kB RAM is available. The RAM is organized as a 2 k x 32

bit array.

The availability of 64 kB or 128 kB of program Flash memory in 2-32 kB or 4-32 kB banks, respectively enables

the designers to implement multiple images of firmware (e.g. one main image + one back-up image) in the device

and the flexibility to execute from either of the banks using appropriate algorithms. It also creates the unique

opportunity for the processor to load a new program and subsequently execute that program without interrupting

power delivery. This feature allows the end user to add new features to the power supply while eliminating any

down-time required to load the new program.

The UCD3138128 adds two additional 32 kB program flash blocks. On the UCD3138128, the boot ROM supports

a dual image configuration where each image contains 64 kB. If the first 64kB has an invalid program, the boot

ROM will check for a valid program in the second 64kB and jump there. The boot ROM also supports a

configuration with a single program occupying the entire 128 kB.

For the UCD3138128, on the fly updates are supported through boot ROM while UCD3138A64 on the fly

updates are supported through boot flash. Detailed procedures can be found in SLUUB54

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