UCD3138A64 datasheet(13/80 Pages) TI

Nome de Peças	UCD3138A64

Descrição Electrónicos	UCD3138x Highly-Integrated Digital Controller For Isolated Power

PDF	80 Pages

Scroll/Zoom	100%

Fabricante Electrônico	TI [Texas Instruments]

Página de início	http://www.ti.com

Logo

13 / 80 page

UCD3138128, UCD3138A64

www.ti.com

SLUSBZ8A – JUNE 2014 – REVISED SEPTEMBER 2014

Timing Requirements (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

t(HIGH)

Clock high period(3)

Cumulative clock low slave extend

t(LOW:SEXT)

time(4)

20 + 0.1

Clock/data fall time

Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15)

300

Cb(5)

20 + 0.1

Clock/data rise time

Fall time tf = 0.9 VDD to (VILmax – 0.15)

300

Cb(5)

Total capacitance of one bus line

400

(3)

t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This

specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).

(4)

t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(5)

Cb (pF)

Figure 1. IC/SMBUS/PMBUS Timing Diagram2

Figure 2. Bus Timing In Extended Mode

Submit Documentation Feedback

Product Folder Links: UCD3138128 UCD3138A64

UCD3138A64 Folha de dados(PDF) 13 Page - Texas Instruments