UCD3138ARMHT datasheet(30/83 Pages) TI

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UCD3138A

SLUSC66B – MARCH 2015 – REVISED MAY 2015

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Table 6-1. Interrupt Priority Table (continued)

MODULE COMPONENT OR

NAME

DESCRIPTION

PRIORITY

CAPTURE_0_INT

24-bit timer control

24-bit Timer capture 0 interrupt

COMP_0_INT

24-bit timer control

24-bit Timer compare 0 interrupt

Mode switched in CPCC module Flag needs to be read

CPCC_INT

Constant power constant current

for details

ADC_CONV_INT

12-bit ADC control

ADC end of conversion interrupt

Analog comparator interrupts, overvoltage detection,

FAULT_INT

Fault Mux interrupt

undervoltage detection, LLM load step detection

DPWM3

Same as DPWM1

DPWM2

Same as DPWM1

1) Every (1 to 256) switching cycles

DPWM1

2) Fault detection

3) Mode switching

DPWM0

Same as DPWM1

EXT_FAULT_INT

External Faults

Fault pin interrupt

SYS_SSI_INT

System Software

System software interrupt

31 (highest)

6.5

DPWM Modes of Operation

The DPWM is a complex logic system which is highly configurable to support several different power

supply topologies. The discussion below will focus primarily on waveforms, timing and register settings,

rather than on logic design.

The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts

over again.

The DPWM logic causes transitions in many digital signals when the period counter hits the target value

for that signal.

6.5.1

Normal Mode

In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of

the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck

topologies. The drawing of the Normal Mode waveforms is shown in Figure 6-1.

Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can

be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the

middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The

Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for

external delays, such as MOSFET and gate driver turn on times.

Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the

beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB.

The other edges are dynamic, so blanking is more difficult.

Cycle Adjust B has no effect in Normal Mode.

Detailed Description

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