S1701 datasheet(33/71 Pages) SII

33 / 71 page

HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION

Rev.3.1_00

S-1701 Series

Seiko Instruments Inc.



Standard Circuit

1. S-1701 Series A/B/C/D/E/F/G/H/J/K/L/M types

VSS

VDOUT

ON/OFF

VIN

CIN

Input

VD output

GND

Single GND

VOUT

VR output

*1. CIN is a capacitor for stabilizing the input.

*2. A ceramic capacitor of 1.0

μF or more can be used for CL.

Figure 26

2. S-1701 Series N/P/Q/R/S/T/U/V/W/X/Y/Z types

VSS

VDOUT

(SENSE)

VIN

CIN

Input

VD output

GND

Single GND

VOUT

VR output

*1. CIN is a capacitor for stabilizing the input.

*2. A ceramic capacitor of 1.0

μF or more can be used for CL.

*3. U/V/W/X/Y/Z types of S-1701 series are no connection.

Figure 27

Caution The above connection diagrams and constants will not guarantee successful operation. Perform

thorough evaluation using the actual application to set the constants.



Condition of Application

Input capacitor (CIN):

1.0

μF or more

Output capacitor (CL):

1.0

μF or more

ESR of output capacitor: 10

Ω or less

Caution Generally a series regulator may cause oscillation, depending on the selection of external parts.

Check that no oscillation occurs in an application that uses the above capacitor.

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