SHORT FORM DATA SHEET

82P33724 REVISION 1 09/23/14

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©2014 Integrated Device Technology, Inc.

Port Synchronizer for IEEE 1588 and

Synchronous Ethernet

82P33724

HIGHLIGHTS

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DPLL1 and DPLL2 can be used on line cards to manage the genera-

tion of synchronous port clocks and IEEE 1588 synchronization sig-

nals based on multiple system backplane references

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DPLL3 can be used on line cards to select incoming line clocks for

use on system backplanes; it can also be used for general purpose

timing applications

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APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to

20 MHz) for: 1000BASE-T and 1000BASE-X ports and to generate

IEEE 1588 time stamp clocks and 1 pulse per second (PPS) signals

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Fractional-N input dividers support a wide range of reference fre-

quencies

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The device can be configured from an external EEPROM after reset

FEATURES

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Differential reference inputs (IN1 to IN4) accept clock frequencies

between 2 kHz and 650 MHz

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Single ended inputs (IN5 to IN6) accept reference clock frequencies

between 2 kHz and 162.5 MHz

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Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any

clock reference input

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Reference monitors qualify/disqualify references depending on activ-

ity, frequency and LOS pins

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Automatic reference selection state machines select the active refer-

ence for each DPLL based on the reference monitors, priority tables,

revertive and non-revertive settings and other programmable settings

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Fractional-N input dividers enable the DPLLs to lock to a wide range

of reference clock frequencies including: 10/100/1000 Ethernet, 10G

Ethernet, OTN, SONET/SDH, PDH, TDM, GSM and GNSS frequen-

cies

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Any reference inputs (IN1 to IN6) can be designated as external sync

pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-

able reference clock input

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FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses

that are aligned with the selected external input sync pulse input and

frequency locked to the associated reference clock input

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DPLL1 and DPLL2 can be configured with bandwidths between 18

Hz and 567 Hz

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DPLL1 and DPLL2 lock to input references with frequencies between

2 kHz and 650 MHz

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DPLL3 locks to input references with frequencies between 8 kHz and

650 MHz

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DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/

OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks

are directly available on OUT1 and OUT8

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DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on

OUT9 and OUT10

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APLL1 and APLL2 can be connected to DPLL1 and DPLL2

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APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or

SONET/SDH frequencies

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Any of eight common TCXO/OCXO frequencies can be used for the

System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,

24.576 MHz, 25 MHz or 30.72 MHz

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The I2C slave, SPI or the UART interface can be used by a host pro-

cessor to access the control and status registers

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The I2C master interface can automatically load a device configura-

tion from an external EEPROM after reset

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Differential outputs OUT3 to OUT6 output clocks with frequencies

between 1 PPS and 650 MHz

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Single ended outputs OUT1, OUT2, OUT7, and OUT8 output clocks

with frequencies between 1 PPS and 125 MHz

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Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi-

ples up to 100 MHz

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DPLL1 and DPLL2 support independent programmable delays for

each of IN1 to IN16; the delay for each input is programmable in

steps of 0.61 ns with a range of ~±78 ns

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The input to output phase delay of DPLL1 and DPLL2 is programma-

ble in steps of 0.0745 ps with a total range of ±20

μs

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The clock phase of each of the output dividers for OUT1 to OUT8 is

individually programmable in steps of ~200 ps with a total range of +/

-180°

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1149.1 JTAG Boundary Scan

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72-pin QFN green package

APPLICATIONS

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Synchronous clock generation for 10/40G and lower rate, Ethernet,

PON OLT and SONET/SDH line card

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Access routers, edge routers, core routers

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Carrier Ethernet switches

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Multiservice access platforms

•PON OLT

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LTE eNodeB