LTC1709_15 datasheet(7/28 Pages) LINER

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LTC1709

Oscillator Frequency

vs Temperature

Undervoltage Lockout

vs Temperature

VRUN/SS Shutdown Latch

Thresholds vs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS

TEMPERATURE (

°C)

–50

–25

0.5

1.5

2.0

2.5

100

4.5

1709 G25

1.0

125

3.0

3.5

4.0

LATCH ARMING

LATCHOFF

THRESHOLD

TEMPERATURE (

°C)

–50

3.40

3.45

3.50

1709 G24

3.35

3.30

–25

100

125

3.25

3.20

TEMPERATURE (

°C)

–50

200

250

350

1709 G23

150

100

–25

100

125

300

VFREQSET = 5V

VFREQSET = OPEN

VFREQSET = 0V

RUN/SS (Pin 1): Combination of Soft-Start, Run Control

Input and Short-Circuit Detection Timer. A capacitor to

ground at this pin sets the ramp time to full current output.

Forcing this pin below 0.8V causes the IC to shut down all

internal circuitry. All functions are disabled in shutdown.

SENSE 1+, SENSE 2+ (Pins 2,14): The (+) Input to Each

Differential Current Comparator. The ITH pin voltage and

built-in offsets between SENSE– and SENSE+ pins in

conjunction with RSENSE set the current trip threshold.

SENSE 1–, SENSE 2– (Pins 3, 13): The (–) Input to the

Differential Current Comparators.

EAIN (Pin 4): Input to the Error Amplifier that compares

the feedback voltage to the internal 0.8V reference voltage.

This pin is normally connected to a resistive divider from

the output of the differential amplifier (DIFFOUT).

PLLFLTR (Pin 5): The Phase-Locked Loop’s Low Pass

Filter is tied to this pin. Alternatively, this pin can be driven

with an AC or DC voltage source to vary the frequency of

the internal oscillator.

PLLIN (Pin 6): External Synchronization Input to Phase

Detector. This pin is internally terminated to SGND with

50k

Ω. The phase-locked loop will force the rising top gate

signal of controller 1 to be synchronized with the rising

edge of the PLLIN signal.

NC (Pins 7, 36): Do not connect.

ITH (Pin 8): Error Amplifier Output and Switching Regula-

tor Compensation Point. Both current comparator’s thresh-

olds increase with this control voltage. The normal voltage

range of this pin is from 0V to 2.4V

SGND (Pin 9): Signal Ground, common to both control-

lers. Route separately to the PGND pin.

VDIFFOUT (Pin 10): Output of a Differential Amplifier that

provides true remote output voltage sensing. This pin

normally drives an external resistive divider that sets the

output voltage.

VOS–, VOS+ (Pins 11, 12): Inputs to an Operational Ampli-

fier. Internal precision resistors capable of being elec-

tronically switched in or out can configure it as a differen-

tial amplifier or an uncommitted Op Amp.

ATTENOUT (Pin 15): Voltage Feedback Signal Resistively

Divided According to the VID Programming Code.

ATTENIN (Pin 16): The Input to the VID Controlled Resis-

tive Divider.

VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic

Input Pins.

VBIAS (Pin 22): Supply Pin for the VID Control Circuit.

PI FU CTIO S

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