LTC1660IGN datasheet(7/16 Pages) LINER

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LTC1665/LTC1660

BLOCK DIAGRA

PIN FUNCTIONS

GND (Pin 1): System Ground.

VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog

Voltage Outputs. The output range is

255

256

1665

1023

1024

1660

for the LTC

REF

















REF (Pin 6): Reference Voltage Input. 0V

≤ VREF ≤ VCC.

CS/LD (Pin 7): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on DIN

into the register. When CS/LD is pulled high, SCK is

disabled and data is loaded from the shift register into the

specified DAC register(s), updating the analog output(s).

CMOS and TTL compatible.

SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL

compatible.

DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin

is shifted into the 16-bit register on the rising edge of SCK.

CMOS and TTL compatible.

DOUT (Pin 10): Serial Interface Data Output. Data appears

on DOUT 16 positive SCK edges after being applied to DIN.

May be tied to DIN of another LTC1665/LTC1660 for daisy-

chain operaton. CMOS and TTL compatible.

CLR (Pin 11): Asynchronous Clear Input. All internal shift

and DAC registers are cleared to zero at the falling edge of

the CLR signal, forcing the analog outputs to zero scale.

CMOS and TTL compatible.

VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

GND

VOUT A

VOUT B

VOUT C

VOUT D

REF

CS/LD

SCK

VCC

VOUT H

VOUT G

VOUT F

VOUT E

CLR

DOUT

DIN

1665/60 BD

DAC A

DAC H

DAC B

DAC G

DAC C

DAC F

DAC D

DAC E

ADDRESS

DECODER

CONTROL

LOGIC

SHIFT REGISTER

(LTC1665/LTC1660)

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