LTC1695CS5 datasheet(14/20 Pages) LINER

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LTC1695

Thermal Considerations

The LTC1695’s power handling capability is limited by the

maximum rated junction temperature of 125

°C. Power

dissipation (PDISS) consists of two components:

1. Output current multiplied by the input/output voltage

differential: (ILOAD)(VCC – VOUT), and

2. GND pin current multiplied by the input voltage:

(IGND)(VCC).

PDISS = (ILOAD)(VCC – VOUT) + (IGND)(VCC)

TJ = PDISS • (θJA)

The LTC1695 has active current limiting and thermal

shutdown circuitry for device protection during overload

or fault condition. For continuous overload conditions, do

not exceed the 125

°C maximum junction temperature

TJ(MAX). Give careful consideration to all thermal resis-

tance sources from junction to ambient. Consider any

additional heat sources mounted in proximity to the

LTC1695. This is particularly relevant in applications

where the LTC1695’s output is loaded with a constant

ILOAD and VOUT is dynamically varied via the SMBus. At

lower DAC output voltage codes, the increased input-to-

output differential increases power dissipation if ILOAD

does not decrease.

For the LTC1695’s 5-lead SOT-23 surface mount package,

heat sinking is accomplished by using the heat spreading

capabilities of the PC board and its copper traces (in

particular, the GND pin trace).

The following table lists measured thermal resistance

results for various size boards and copper areas. All

measurements were taken in still air on 3/32" FR-4 board

with one ounce copper.

Table 2. Measured Thermal Resistance (

θθθθθJA)

Topside*

Backside

Board Area

2500mm2

125

°C/W

1000mm2

2500mm2

125

°C/W

225mm2

2500mm2

130

°C/W

100mm2

2500mm2

135

°C/W

50mm2

2500mm2

150

°C/W

*Device is mounted on topside

–

OP AMP

CGATE

CNODE

VCC

VOUT

LFAN

CFAN

COUT

ESR

GND

EQUIVALENT

DC FAN CIRCUIT

INTERNAL

DAC

OUTPUT

P1(0.75

Ω)

1695 • F04

Figure 4. Regulator Feedback Loop

capacitance ranges from 2pF to 30pF. As previously

discussed, an output bypass capacitor is required to

stabilize the feedback loop. This output capacitor is in

parallel with the fan’s input capacitance and dominates the

total capacitance. Thus, stability is generally not affected

by the fan’s input capacitance. The output capacitor also

serves to filter the fan’s output ripple during commutation

of the fan’s motor.

POR and UVLO

Under start-up conditions, the LTC1695 performs a power

on reset (POR) function. The digital logic circuitry is

disabled and the regulator is held off. The SMBus com-

mand register (to the DAC’s input) and data register

(current limit and thermal shutdown status) are reset to

zero. The POR signal deactivates if VCC rises above 2.9V

typically. The LTC1695 is then allowed to communicate

with the SMBus host and drive the fan accordingly. Upon

exiting POR, the regulator’s output voltage is set to VZS

(code 0) until programmed by the SMBus host.

The LTC1695 enters UVLO if VCC falls below 2.8V typically.

Between 2.8V and 1V, the digital logic circuitry is disabled,

the command/data registers are cleared and the regulator

is shut down. In general, 100mV of hysteresis exists

between the UVLO and POR thresholds.

APPLICATIONS INFORMATION

Thermal Resistance

(Junction to Ambient)

Copper Area

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