LTC2229_15 datasheet(8/24 Pages) LINER

8 / 24 page

LTC2229

2229fa

PI FU CTIO S

AIN+ (Pin 1): Positive Differential Analog Input.

AIN- (Pin 2): Negative Differential Analog Input.

REFH (Pins 3, 4): ADC High Reference. Short together and

bypass to pins 5, 6 with a 0.1

µF ceramic chip capacitor as

close to the pin as possible. Also bypass to pins 5, 6 with

an additional 2.2

µF ceramic chip capacitor and to ground

with a 1

µF ceramic chip capacitor.

REFL (Pins 5, 6): ADC Low Reference. Short together and

bypass to pins 3, 4 with a 0.1

µF ceramic chip capacitor as

close to the pin as possible. Also bypass to pins 3, 4 with

an additional 2.2

µF ceramic chip capacitor and to ground

with a 1

µF ceramic chip capacitor.

VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF

ceramic chip capacitors.

GND (Pin 8): ADC Power Ground.

CLK (Pin 9): Clock Input. The input sample starts on the

positive edge.

SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-

ing SHDN to GND and OE to GND results in normal

operation with the outputs enabled. Connecting SHDN to

GND and OE to VDD results in normal operation with the

outputs at high impedance. Connecting SHDN to VDD and

OE to GND results in nap mode with the outputs at high

impedance. Connecting SHDN to VDD and OE to VDD

results in sleep mode with the outputs at high impedance.

OE (Pin 11): Output Enable Pin. Refer to SHDN pin

function.

NC (Pins 12, 13): Do Not Connect These Pins.

D0–D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,

27): Digital Outputs. D11 is the MSB.

OGND (Pin 20): Output Driver Ground.

OVDD (Pin 21): Positive Supply for the Output Drivers.

Bypass to ground with 0.1

µF ceramic chip capacitor.

OF (Pin 28): Over/Under Flow Output. High when an over

or under flow has occurred.

MODE (Pin 29): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to GND selects

offset binary output format and turns the clock duty cycle

stabilizer off. 1/3 VDD selects offset binary output format

and turns the clock duty cycle stabilizer on. 2/3 VDD selects

2’s complement output format and turns the clock duty

cycle stabilizer on. VDD selects 2’s complement output

format and turns the clock duty cycle stabilizer off.

SENSE (Pin 30): Reference Programming Pin. Connecting

SENSE to VCM selects the internal reference and a ±0.5V

input range. VDD selects the internal reference and a ±1V

input range. An external reference greater than 0.5V and

less than 1V applied to SENSE selects an input range of

±VSENSE. ±1V is the largest valid input range.

VCM (Pin 31): 1.5V Output and Input Common Mode Bias.

Bypass to ground with 2.2

µF ceramic chip capacitor.

GND (Exposed Pad) (Pin 33): ADC Power Ground. The

exposed pad on the bottom of the package needs to be

soldered to ground.

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