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UPD75512 Folha de dados(PDF) 21 Page - NEC |
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UPD75512 Folha de dados(HTML) 21 Page - NEC |
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21 / 64 page ![]() µPD75512(A) 21 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote control output, peripheral LSIs, etc. • Clock output (PCL): Φ, 524 kHz, 262 kHz, 65.5 kHz (operating at 4.19 MHz) Fig. 5-2 Clock Output Circuit Configuration Remarks: A measures to prevent outputting narrow width pulse when selecting clock output enable/ disable is taken. Selector Output buffer PCL/P22 Bit 2 of PMGB PORT2.2 Port 2 input/ output mode specification bit P22 output latch Internal bus CLOM3 CLOM2 CLOM1 CLOM0 CLOM 4 Φ fX/23 fX/24 fX/26 From the clock generator |
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