AN4570 datasheet(23/46 Pages) STMICROELECTRONICS

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AN4570

Interfacing with a non-multiplexed, asynchronous 16-bit SRAM

Figure 7. SRAM asynchronous write access timing

3.1.1

Typical use of the FMC to interface with an SRAM

In this application note, the IS61WV51216BLL memory is used as the reference.

The IS61WV51216BLL memory is a non-multiplexed, asynchronous, 16-bit memory. Bank3

is selected to support the SRAM device. Based on these data, the FMC is configured as

follows:

•

Bank3 is enabled: BCR3_MBKEN bit set to ‘1’

•

Memory type is SRAM: BCR3_MTYP is set to ‘00’ to select the SRAM memory type

•

Data bus width is 16 bits: BCR3_MWID is set to ‘01’ to select the 16-bit width

•

The memory is non-multiplexed: BCR3_MUXEN is reset

All remaining parameters must be kept cleared.

3.2

Timing computation

The SRAM shares the same banks and configuration register as the NOR Flash memory.

As a result, the timing computation method is the same as described in detail in the NOR

Flash section (Section 2.2: Timing computation on page 11).

The FMC is configured on the basis of the SRAM access timings illustrated in Figure 6 and

Figure 7, and taking into account the following:

•

the maximum read/write access time

•

the different internal FMC delays

•

the different internal memory delays

Hence the following equations:

((ADDSET + 1) + (DATAST + 1)) × tHCLK

≥ max (tWC)

DATAST × tHCLK = tPWE1

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