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ST9 USER GUIDE

3.6.1.3 Low Power with Frequency Slow Down

When the PLL has been frozen by a WFI instruction you need a delay after the interrupt to wait

for the PLL to lock. To avoid this delay but not to lose the Low Power consumption, you have

two choices which are:

– To use a WFI instruction with LPOWFI reset and initialize INTCLK to CLOCK2 with

XT_DIV16 bit set (CSU_CKSEL register). When the WFI occurs, CPUCLK is stopped and

INTCLK doesn’t change.

– To not use the WFI instruction. Set XT_DIV16 bit of CSU_CKSEL register. Initialize DX2:0

of PLLCONF to 6 to divide the PLL output clock by 7 which is the maximum. Initialize the

CPUCLK clock prescaler to 7 to divide INTCLK by 8.

3.6.2 Reset and Stop Manager

RESET normally means restarting from the beginning with everything initialized. However

sometimes it’s necessary to know the context of the ST9 before the RESET and if it was an ex-

ternal or internal RESET. Two bits, SOFTRES and WDGRES in the CLK_FLAG register indi-

cate the previous context. Table 3. shows the three cases to manage.

Table 3.

Three Types of RESET

These bits are read-only and change with each Reset.

RESET Type

SOFTRES bit

WDGRES bit

Meaning

External RESET

High to low level on RESET pin.

Watchdog RESET

The Watchdog Timer is activated and the Timer

has reached 0.

Software RESET

The HALT instruction is executed, waiting for an

external Reset to restart (if the SRESEN bit in the

CLKCTL register is set).

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