PM0056 datasheet(21/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 processor

Base priority mask register

The BASEPRI register defines the minimum priority for exception processing. When

BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or

lower priority level as the BASEPRI value. See the register summary in Table 2 on page 14

for its attributes. Figure 7 shows the bit assignments.

Figure 7. BASEPRI bit assignments

CONTROL register

The CONTROL register controls the stack used and the privilege level for software

execution when the processor is in Thread mode. See the register summary in Table 2 on

page 14 for its attributes. Figure 8 shows the bit assignments.

Figure 8. CONTROL bit assignments

Table 9. BASEPRI register bit assignments

Bits

Function

Bits 31:8

Reserved

Bits 7:4

BASEPRI[7:4] Priority mask bits(1)

0x00: no effect

Nonzero: defines the base priority for exception processing.

The processor does not process any exception with a priority value greater than or

equal to BASEPRI.

1. This field is similar to the priority fields in the interrupt priority registers. See Interrupt priority registers

(NVIC_IPRx) on page 125 for more information. Remember that higher priority field values correspond to

lower exception priorities.

Bits 3:0

Reserved

Table 10. CONTROL register bit definitions

Bits

Function

Bits 31:2

Reserved

BASEPRI

Reserved

210

Reserved

Active stack pointer

Thread mode privilege level

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