AN3961 datasheet(21/46 Pages) STMICROELECTRONICS

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AN3961

Hardware layout and configuration

Data required to generate a program are stored in the SPI Flash memory. When the

program starts, data are downloaded from Flash memory and stored in FPGA internal RAM

blocks. Then data is managed in order to generate the high-speed STHV748 digital control

signals.

The SPI Flash also contains the FPGA configuration data (“bit stream”) which are

automatically loaded during startup and after the FPGA reset (SW5) is pressed.

The FPGA is configured by setting jumpers as described in Table 6.

Table 5. Program waveforms main features

Feature

Min.

Typ.

Max.

Waveform number

Time resolution

5 ns

Duration

40 ns

20.48 µs

Cycles number

255

Infinite cycle

Defined by the program

Table 6. FPGA jumpers

Description

J5 is used to control FPGA I/O pull-ups during configuration. It should be fitted to enable

I/O pull-ups during FPGA configuration.

Default setting: not mounted.

J12

Force FPGA into suspend mode

Allow the STM32 to control FPGA suspend mode

(default setting)

J13

J13 is used to prevent FPGA programming from configuration source.

Fitted: disable FPGA programming.

Unfitted: enable FPGA programming.

(default setting: unfitted)

J35 and

J36

Configure J35 and J36 to set up the outputs idle state as follows:

(default setting: not mounted)

High Z

Clamp / HVR_SW

High Z

Clamp

J37

Configure J37 to connect FPGA outputs to STHV748

(default setting: not mounted)

Fitted: disconnect FPGA outputs (high Z)

Unfitted: connect FPGA outputs

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