AN2282

Hardware

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Figure 5.

STR7 EMI read timing diagram

Figure 6.

STR7 EMI write timing diagram

CS8900A timing diagrams for memory mode access are the same so they are not included

in this document.

Considering the MCLK value is equal to 48 MHz and 7 wait states, the cycle times are as

follows:

a)

b)

c)

d)

e)

f)

All cycle times are compatible with Ethernet controller timing. Of course it also possible to

use more than 7 wait states.

Considering the data bus connection of Figure 2, the STR7 reads incoming data in Little

Endian byte order. For example assume that the data received from the Ethernet wire is

0x01, 0x02, 0x03, 0x04, etc. where 0x01 is the first byte, 0x02 the second and so on; STR7

reads the following data words: 0x0201, 0x0403, etc.

A[23:0]

RDn

CSn.x

WEn.x

D[15:0]

(input)

Address

Address

A[23:0]

RDn

CSn.x

WEn.x

D[15:0]

(output)

Data Output