LTC4403-1_15 datasheet(5/12 Pages) LINER

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LTC4403-1/LTC4403-2

4403f

APPLICATIONS INFORMATION

Operation

The LTC4403-1/-2 single/dual band RF power controller

integrates several functions to provide RF power control

over frequencies ranging from 300MHz to 2.4GHz. These

functions include an internally compensated amplifier to

control the RF output power, an autozero section to cancel

internal and external voltage offsets, an RF Schottky diode

peak detector and amplifier to convert the RF feedback

signal to DC, a multiplexer to switch the controller output

to either VPCA or VPCB, a VPCA/B overvoltage clamp, com-

pression and a bandgap reference.

Band Selection

The LTC4403-2 is designed for multiband operation. The

BSEL pin will select output VPCA when low and output

VPCB when high. For example, VPCA could be used to drive

an 850MHz/900MHz channel and VPCB a 1.8GHz/1.9GHz

channel. BSEL must be established before the part is

enabled. The LTC4403-1 can be used to drive a single RF

channel or dual channel with integral multiplexer.

Control Amplifier

The control amplifier supplies the power control voltage to

the RF power amplifier. A portion (typically – 19dB for low

frequencies and –14dB for high frequencies) of the RF

output voltage is coupled into the RF pin, to close the gain

control loop. When a DAC voltage is applied to PCTL, the

amplifier quickly servos VPCA or VPCB positive until the

detected feedback voltage applied to the RF pin matches

the voltage at PCTL. This feedback loop provides accurate

RF power control. VPCA or VPCB are capable of driving a

6mA load current and 100pF load capacitor.

RF Detector

The internal RF Schottky diode peak detector and ampli-

fier convert the coupled RF feedback voltage to a low

frequency voltage. This voltage is compared to the DAC

voltage at the PCTL pin by the control amplifier to close

the RF power control loop. The RF pin input resistance is

typically 250

Ω and the frequency range of this pin is

300MHz to 2400MHz. The detector demonstrates excel-

lent efficiency and linearity over a wide range of input

power. The Schottky detector is biased at about 60

µA and

drives an on-chip peak detector capacitor of 28pF.

Autozero

An autozero system is included to improve power pro-

gramming accuracy over temperature. This section can-

cels internal offsets associated with the Schottky diode

detector and control amplifier. External offsets associated

with the DAC driving the PCTL pin are also cancelled.

Offset drift due to temperature is cancelled between each

burst. The maximum offset allowed at the DAC output is

limited to 400mV. Autozeroing is performed after SHDN

is asserted high. An internal delay of typically 9

µs enables

the VPCA/B output after the autozero has settled. When the

part is enabled, the autozero capacitors are held and the

VPCA or VPCB pin is connected to the buffer amplifier

output. The hold droop voltage of typically < 1

µV/ms

provides for accurate offset cancellation.

Filter

There is a 270kHz filter included in the PCTL path. This

filter is trimmed at test.

Modes of Operation

Shutdown: The part is in shutdown mode when SHDN is

low. VPCA and VPCB are held at ground and the power

supply current is typically 10

µA.

Enable: When SHDN is asserted high the part will auto-

matically calibrate out all offsets. This takes about 9

µs and

is controlled by an internal delay circuit. After 9

µs VPCA or

VPCB will step up to the starting voltage of 450mV. The

user can then apply the ramp signal. The user should wait

at least 11

µs after SHDN has been asserted high before

applying the ramp. The DAC should be settled 2

µs after

asserting SHDN high.

Hold: When the VHOLD pin is low, the RF power control

feedback loop is closed and the LTC4403-X servos the

VPCA/VPCB pins according to the voltages at the PCTL and

RF inputs. When the VHOLD pin is asserted high, the RF

power control feedback loop is opened and the power

control voltage at VPCA or VCPB is held at its present level.

Generally, the VHOLD pin is asserted high after the power

up ramp has been completed and the desired RF output

power has been achieved. The power control voltage is

then held at a constant voltage during the EDGE modula-

tion time. After the EDGE modulation is completed and

prior to power ramping down, the VHOLD pin is set low.

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