AN2014 datasheet(19/65 Pages) STMICROELECTRONICS

19 / 65 page

DocID10701 Rev 10

19/65

AN2014

Recommendations to improve EEPROM reliability

3.2

Electrical overstress and latchup

Electrical overstress (EOS) and latchup are also damaging stresses that are either

immediately destructive, or may create latent defects leading to premature failure.

3.2.1

What are EOS and latchup?

In comparison with ESDs, EOS and latchup are lower-intensity events that last much longer

(sometimes more than a few seconds). That is why the energy induced by an EOS is higher

than the ESD energy. EOS and latchup induce current injections inside the EEPROM when

an overvoltage stress is applied on one or more package pins. Latchup occurs when a

charge injection triggers the I/O parasitic thyristors (also called SCR) thus generating a very

high current between VDD and VSS. This phenomenon lasts until the VCC power supply is

turned off.

3.2.2

How to prevent EOS and latchup events

Typically power supply cycling leads to EOS situations. During the power-up and power-

down phases, the EEPROM I/Os interfaced with other ICs may temporary see voltages

greater than VCC or lower than VSS. When outside Absolute Maximum Ratings, these

biasing conditions may lead to positive and negative current injections, respectively. This

kind of stress cannot always be completely prevented but it can be minimized. The

switching sequence of the different interfaced ICs must be carefully determined, and if

necessary protection resistor (<1K

Ω) can be placed on critical pins or sometimes directly on

VCC pin (<50Ω) to limit eventual latchup current. Please refer to Section 4: Hardware

considerations for more details.

Overshoots and undershoots may occur on external device pins when the application is

running. They can be generated by radiations, power supply disturbances or even some

ICs. The very first protection is provided by the semiconductor manufacturer (ST) which

offers the best possible robustness against EOS and latchup. If extra protection is needed,

the application designer can add small value resistors (<1k

Ω) in series on all interfaced lines

and (<50Ohm) in series on

VCC line so that it can be compatible with the communication speed

constraints and power supply range. Please refer to the Hardware considerations section for

more details.

Manufacturing and handling devices are also sources of EOS: all voltage levels applied to

the device must be checked accurately and regularly. In addition all equipment should be

constantly calibrated.

During write operations, an EEPROM device is more sensitive to overvoltages on its power

supply pin because the internal high voltage generator is directly fed by the voltage applied

to the power supply pin.

AN2014 Folha de dados(PDF) 19 Page - STMicroelectronics

AN2014 Folha de dados(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Folha de dados Download

Ligação URL