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AN3393 Folha de dados(PDF) 53 Page - STMicroelectronics

Nome de Peças AN3393
Descrição Electrónicos  This document is intended to provide information
PDF  103 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN3393 Folha de dados(HTML) 53 Page - STMicroelectronics

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AN3393
Operation codes
103
6.1.10
GTTH1 (9h)
The GTTH1 condition is valid if any/triggered axis of data sample set (X, Y, Z, V) is greater
than threshold 1 level. The GTTH1 condition always evaluates the standard axis mask
(MASK1).
Threshold is: THRS1_y + Hysteresis.
Hysteresis is:
–
State Machine 1: CTRL_REG1, bits HYST2_1, HYST1_1 and HYST0_1;
–
State Machine 2: CTRL_REG2, bits HYST2_2, HYST1_2 and HYST0_2.
This condition affects or is affected by the following registers:
–
THRS1_y: Threshold 1 value;
–
MASK1_A and MASK1_B: Axis mask filter values;
–
SETT1, bit ABS: Unsigned/signed settings;
–
SETT1, bit P_DET: Peak detection settings;
–
PEAK1: Peak output value;
–
PR1: Program and Reset pointer addresses;
–
Note: R_TAM bit in SETT1 register does not affect this condition, since the
standard mask is always evaluated.
6.1.11
LLTH2 (Ah)
The LLTH2 condition is valid if all axes in data sample set (X, Y, Z, V) are less than or equal
to threshold 2 level.
Threshold is: THRS2_y - Hysteresis.
Hysteresis is:
–
State Machine 1: CTRL_REG1, bits HYST2_1, HYST1_1 and HYST0_1;
–
State Machine 2: CTRL_REG2, bits HYST2_2, HYST1_2 and HYST0_2.
This condition affects or is affected by the following registers:
–
THRS2_y: Threshold 2 value;
–
MASKy_A and MASKy_B: Axis mask filter values;
–
SETTy, bit ABS: Unsigned/signed settings;
–
SETTy, bit R_TAM: Release temporary output mask settings;
–
SETTy, bit P_DET: Peak detection settings;
–
PEAKy: Peak output value;
–
PRy: Program and Reset pointer addresses.
6.1.12
GRTH1 (Bh)
The GRTH1 condition is valid if any/triggered axis of data sample set (X, Y, Z, V) is greater
than reversed threshold 1 level.
Threshold is: THRS1_y + Hysteresis.
Hysteresis is:
–
State Machine 1: CTRL_REG1, bits HYST2_1, HYST1_1 and HYST0_1;
–
State Machine 2: CTRL_REG2, bits HYST2_2, HYST1_2 and HYST0_2;



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