AN3308 datasheet(46/52 Pages) STMICROELECTRONICS

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First in first out (FIFO) buffer

AN3308

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Doc ID 18198 Rev 1

In Figure 26, due to slow reading, data from “jj” are not retrieved because they are replaced

by the new accelerometer samples generated by the system.

Figure 27.

Stream mode slow reading zoom

After stream mode enable, FIFO slots are filled at the end of each ODR time frame. The

reading procedure must start as soon as the OVRN flag is set to “1”, data are retrieved from

FIFO at the beginning of the reading operation. When a read command is sent to the device,

the output registers content is moved to the SPI/I2C register and the current oldest FIFO

value is shifted into the output registers in order to allow the next read operation. In the case

of a reading slower than 1*ODR, some data can be retrieved from FIFO after that new

sample is inserted into the addressed location. In Figure 27 the fourth read command starts

after the refresh of the F3 index and this generates a disconnect in the reading data. The

OVRN flag advises the user that this event has taken place. In this example, three correct

samples have been read, the number of correctly recovered samples is dependent on the

difference between the current ODR and the FIFO sample set reading timeframe.

9.3.4

Stream-to-FIFO mode

This mode is a combination of the stream and FIFO modes described above. In stream-to-

FIFO mode, the FIFO buffer starts operating in stream mode and switches to FIFO mode

when the selected interrupt occurs.

Follow these steps for stream-to-FIFO mode configuration:

Configure desired interrupt generator using register INT1_CFG (0x30).

Set TRen bit in the FIFO control register (0x2E) according to the configured interrupt

generator: TRen = “0” in order to select interrupt 1, TRen = “1” in order to select

interrupt 2.

Turn on FIFO by setting the FIFO_En bit to “1” in control register 5 (0x24). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are frozen

to the last samples set loaded.

Activate stream-to-FIFO mode by setting the FN[1:0] field to “11” in the FIFO control

The interrupt trigger is related to the IA bit in the INT1_SRC register and it is generated even

if the interrupt signal is not driven to an interrupt pad. Mode switch is performed if both IA

and OVRN bits are set high. Stream-to-FIFO mode is sensitive to the trigger level and not to

the trigger edge, this means that if stream-to-FIFO is in FIFO mode and the interrupt

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