UPD17708 datasheet(147/356 Pages) NEC

147 / 356 page

147

µPD17704, 17705, 17707, 17708, 17709

Table 12-3. Issuance of Interrupt Request by Changing IEG Flag

Changes in IEG0 through IEG4 Flags Status of INT0 through INT4 Pins

Issuance of Interrupt Request

Status of Interrupt Request Flag

→

Low level

Not issued

Retains previous status

(Falling) (Rising)

High level

Issued

Set to “1”

→

Low level

Issued

Set to “1”

(Rising) (Falling)

High level

Not issued

Retains previous status

12.9.3 Interrupt control block

The signal levels that are input to the INT0 through INT4 pins can be detected by using the INT0 through INT4

flags.

Because these flags are reset independently of interrupts, when the interrupt function is not used the INT0

through INT2 pins can be used as a 3-bit input port, and P1A2/INT3 and P1A3/INT4 pins can be used as a 2-

bit general-purpose input port.

If the interrupts are not enabled, these ports can be used as general-purpose port pins whose rising or falling

edge can be detected by reading the corresponding interrupt request flags.

At this time, however, the interrupt request flags are not automatically reset and must be reset by the program.

For further information, also refer to 12.2.1 Configuration and function of interrupt request flag (IRQ

×××).

12.10 Internal Interrupts

The following six internal interrupts are available.

•

Timer 0

•

Timer 1

•

Timer 2

•

Timer 3

•

Serial interface 0

•

Serial interface 1

12.10.1 Timer 0, timer 1, timer 2, and timer 3 interrupts

Interrupt requests are issued at fixed intervals.

For details, refer to 13. TIMER.

12.10.2 Serial interface 0 and serial interface 1 interrupts

Interrupt requests can be issued at the end of a serial output or serial input operation.

For details, refer to 16. SERIAL INTERFACE.

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