Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

Preview PDF HTML

UPD17708 Folha de dados(PDF) 300 Page - NEC

Nome de Peças UPD17708
Descrição Electrónicos  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  NEC [NEC]
Página de início  http://www.nec.com/
Logo NEC - NEC

UPD17708 Folha de dados(HTML) 300 Page - NEC

Back Button UPD17708 Datasheet HTML 296Page - NEC UPD17708 Datasheet HTML 297Page - NEC UPD17708 Datasheet HTML 298Page - NEC UPD17708 Datasheet HTML 299Page - NEC UPD17708 Datasheet HTML 300Page - NEC UPD17708 Datasheet HTML 301Page - NEC UPD17708 Datasheet HTML 302Page - NEC UPD17708 Datasheet HTML 303Page - NEC UPD17708 Datasheet HTML 304Page - NEC Next Button
Zoom Inzoom in Zoom Outzoom out
 300 / 356 page
background image
300
µPD17704, 17705, 17707, 17708, 17709
Figure 20-3. Stop Releasing Conditions
Operand
STOP s (4 bits)
b3 b2
b1 b0
0
1
Releases when high level is input to port 0D
Undefined (Fix this bit to “0”.)
Undefined (Fix this bit to “0”.)
Released by interrupt of falling edge of INT0 through INT4 pins and CE pin
Not released even if condition is statisfied
Released if condition is satisfied
Specifies stop status releasing condition
The “STOP s” instruction is executed as a “NOP” instruction when the CE pin rises and when the CE reset counter
operates.
The operating status of the CE reset counter can be detected by the CECNTSTT flag (for the CE reset counter,
refer to 21. RESET).
20.3.4 Releasing clock stop status by high level input of port 0D
Figure 20-4 illustrates how the clock stop status is released by the high level input to port 0D.
Figure 20-4. Releasing Clock Stop Status By High Level Input of Port 0D
VDD
P0D
XOUT
5 V
0 V
H
L
2.2 V
STOP s instruction
Starts from instruction next to
STOP s
Oscillation stops
tSET/2
HALT period
tSET: basic timer 0 setting time
20.3.5 Cautions on releasing clock stop status
For the cautions on releasing the clock stop status, refer to (2) Releasing from clock stop status in 21.4.4
Cautions on raising supply voltage VDD.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Folha de dados Download

Go To PDF Page


Ligação URL



ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   Link para a ficha técnica    |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com