UPD17708 datasheet(249/356 Pages) NEC

249 / 356 page

249

µPD17704, 17705, 17707, 17708, 17709

16.3.6 Operation of serial interface 1

(1) Timing chart

Figure 16-19 shows the timing chart.

Figure 16-19. Timing Chart of Serial Interface 1

Shift clock

Serial data

<1>

<2>

<3>

INT <5>

<4>

Clock counter

SIO1TS

<1> Initial status (general-purpose input port)

<2> Sets transmission status of master/releases wait status

<3> Wait timing

<4> Releases wait status again

<5> Interrupt issuance timing

(2) Operation of clock counter

The value of the clock counter is incremented from the initial value “0” each time the rising of the clock pin

has been detected.

The value of the clock counter returns to “0” after it has reached “8”, and the clock counter continues counting.

The clock counter is also reset in the following cases.

•

At reset (power-ON reset, WDT&SP reset, CE reset)

•

On execution of clock stop instruction

•

If “0” is written to SIO1TS flag

(3) Wait operation and cautions

When the wait status is released, serial data is output (during transmission operation) at the falling of the next

clock, and the wait status is released at the eighth clock.

After eight clocks have been output, the shift clock pin is made high, and the operations of the clock counter

and presettable shift register 1 are stopped.

The value of the presettable shift register 1 cannot be read correctly if it is read while the wait status is released

and while the shift clock pin is high.

Correct data cannot be written to the presettable shift register 1 while the wait status is released and while

the shift clock pin is low.

If the forced wait status is specified while the wait status is released, the forced wait status is set as soon as

“0” has been written to the SIO1TS flag, and the clock counter is reset.

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