AN1978 - APPLICATION NOTE

9/14

Figure 11: OFF behaviour on VDD drop.

Figure 12: Deactivation sequence automatically when spikes on VDD are present.

Conditions:

V

V

V

5/3V=L.

CH1:CMDVCC

CH2: VDD

CH3: OFF

CH4: Vcc

When the V

the Vth2 value (about 2.1V) a

deactivation sequence starts and

the OFF pin goes low until

CMDVCC rising edge happens.

Conditions:

V

V

V

5/3V=H.

CH1: Vcc

CH2: V

CH3: RST pin.

When the V

down the Vth3 value (about

3.0V) for more than 20

µs. a

deactivation

sequence

starts; the RST pin (CH3) is

the first that goes low.

Conditions:

V

V

V

5/3V=H.

CH1: Vcc

CH2: V

CH3: RST pin.

When the V

down the Vth3 value (about

3.0V) for more than 20

µs. a

deactivation

sequence

starts; the RST pin (CH3) is

the first that goes low.