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e200z3 core complex overview

UM0434

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e200z3 core complex overview

This chapter provides an overview of the PowerPC™ e200z3 microprocessor core. It

includes the following:

●

An overview of the Book E version of the PowerPC architecture features as

implemented in this core

●

A summary of the core feature set

●

An overview of the programming model

●

An overview of interrupts and exception handling

●

A summary of instruction pipeline and flow

●

A description of the memory-management architecture

●

High-level details of the e200z3 core memory and coherency model

●

A summary of the Book E architecture compatibility and migration from the original

version of the PowerPC architecture as it is defined by Apple, IBM, (referred to as the

AIM version of the PowerPC architecture)

●

Information regarding e200z3 features that are defined by the Book E implementation

standards (EIS)

3.1

Overview of the e200z3

The e200z3 processor family is a set of CPU cores that are low-cost implementations of the

PowerPC Book E architecture. e200z3 processors are designed for deeply embedded

control applications that require low-cost solutions rather than maximum performance.

The e200z3 core implements the variable-length encoding (VLE) APU, providing improved

code density. See the

EREF for more information about the VLE extension.

Figure 1.

e200z3 block diagram

Instruction Bus Interface Unit

Software-Managed

Unified Memory Unit

MAS

Registers

32 GPRs

(64-Bit)

XER

4-, 16-, 64-,

256-Kbyte;

Execution Units

SPRs

Integer

+ x ÷

Unit

SPE APU

+ x ÷

Unit

Embedded

+ x ÷

Scalar FPU

Embedded

+ x ÷

Vector FPU

Load/Store

Branch

Unit

Write-Back Stage

Two/Four

instructions

Address

Data

Control

Additional

Features

–OnCe/Nexus

1/Nexus 3

control logic

– AMBA AHB-

Lite bus

L1 Unified MMU

Unit

CTR

Single-instruction, in-order dispatch

Single-Instruction, In-Order Write Back

•

16-Entry

Fully Associative

TLB

EA Calc

Four-cycle,

single-path

execute stage

with overlapped

execution and

Fetch Unit

Branch Processing Unit

Instruction/Control Unit

Instruction Buffer

(7 instructions)

Decode

8-Entry Branch

Stage

EA Calc

Two-Cycle

Fetch Stage

Program Counter

Target Buffer

Data Bus Interface Unit

Address

Data

Control

Optional

Extension

VLE

APU

Execute Stage

feed forwarding

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