AN4035 datasheet(18/42 Pages) STMICROELECTRONICS

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On-Chip Emulation (OnCE)

AN4035

18/41

Doc ID 022669 Rev 2

Figure 9 shows writing the value 0b00_0011_0001 to OCMD through the IR path to select a

write to DBCR0 assuming the TAP controller state machine is initially in the RUN-

TEST/IDLE state. The state machine is returned to the RUN-TEST/IDLE state when the

write is complete.

Figure 9.

Signal transitions for writing OCMD to select a write to DBCR0

Figure 10 shows writing the value 0x80000000 to DBCR0 through the DR path to set the

EDM bit assuming the TAP controller state machine is initially in the RUN-TEST/IDLE state.

The state machine is returned to the RUN-TEST/IDLE state when the write is complete.

Figure 10.

Signal transitions for writing DBCR0

3.3.2

Example of OnCE register read

OnCE registers can be read by selecting the register using the RS[0:6] field and setting the

R/W bit in the OnCE command register (OCMD). This requires a scan through the IR path of

the TAP controller state machine to write the OCMD and a scan through the DR path of the

TAP controller state machine to read the selected register. This read example reads DBCR0

after the EDM bit is set.

Figure 11 shows writing the value 0b10_0011_0001 to OCMD through the IR path to select

a read from DBCR0 assuming the TAP controller state machine is initially in the RUN-

TEST/IDLE state. The state machine is returned to the RUN-TEST/IDLE state when the

write is complete.

Data starts on

this clock edge

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